Field Programmable Gate Arrays for Radar Front - End Digital Signal Processing

As field programmable gate array (FPGA) technology has steadily improved, FPGAs have become viable alternatives to other technology implementations for high-speed classes of digital signal processing (DSP) applications. In particular, radar front-end signal processing, an application formerly dominated by custom very large scale integration (VLSI) chips, may now be a prime candidate for migration to FPGA technology. As this thesis demonstrates, current FPGA devices have the power and capacity to implement a FIR filter with the performance and specifications of an existing, in-system, front-end signal processing custom VLSI chip. A 512-tap, 18-bit FIR filter was built that could achieve sample rates of 7 MHz (with a clock rate of 117 MHz) using Xilinx Virtex FPGA technology, and was demonstrated through simulation and hardware implementation. Distributed arithmetic, bit-level systolic arrays, parallel multiplier/accumulator (MAC) cells, fast FIR algorithms, and frequency domain filtering were investigated to determine the most optimal structure for a FPGA FIR design, with distributed arithmetic resulting in the best performance. A custom VHDL cell-based layout tool was designed to improve the placement strategies of the Xilinx FPGA place and route tools, and improved the speed performance of the distributed arithmetic design by 37%. Thesis Supervisors: David R. Martinez Group Leader, Digital Radar Technology Group, MIT Lincoln Laboratory Saman P. Amarasinghe Assistant Professor, MIT Laboratory for Computer Science